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Complex Digital ASIC Design

Description:

This course aims to provide a strong foundation for students to understand the principle and practice of designing, implementing, testing, and evaluating complex standard-cell ASIC chips using automated state-of-the-art electronic design automation (EDA) tools. This course is at the intersection of computer architecture, digital circuits, and EDA and is suitable for students pursuing careers in both research and industry. For students pursuing research topics in computer architecture, the course will provide deeper insight into critical physical design issues for future computing systems, while for students pursuing research topics in digital circuits, the course will provide system-level insight into future large-scale chip designs. For students pursuing a career in the chip-design industry, the course will provide valuable design experience from architecture to digital circuits. The course is divided into four parts: the first three parts are lecture-based, while the final part is an extensive design project. The first part provides an overview of ASIC design including: hardware description languages; CMOS devices; CMOS circuits; full-custom design methodology; automated design methodologies; testing and verification; packaging and I/O. The second part provides a deeper study of CMOS digital-circuit fundamentals including combinational logic, sequential state, and interconnect. The third part provides a deeper study of EDA algorithms including synthesis algorithms and physical design automation algorithms. The final part is an open-ended design project where small groups of students design, implement, test, and evaluate an interesting technique in computer architecture using functional-, microarchitectural-, register-transfer-, and layout-level modeling. This five-week long design experience will include weekly project meetings with the course instructors, milestone documents, a project demonstration, and a detailed final report.

Course Code: ECE 5745

Level: Level 6 (BSc)

Organisations: Cornell University

Target Audience

This course is targeted towards advanced senior undergraduates, M.Eng. students, and first-year Ph.D. students.

Learning Aims:

• Describe concepts related to the overall ASIC design methodology, CMOS digital circuits, and CAD algorithms and explain how these concepts interact

• Apply this understanding to new ASIC design problems within the context of balancing application requirements against technology constraints; more specifically, quantitatively assess a design's execution time in cycles, cycle time, area, and energy

• Evaluate various design alternatives and make a compelling quantitative and/or qualitative argument for why one design is superior to the other approaches

• Demonstrate the ability to implement and verify designs of varying complexity at the register-transfer level and to push these designs through a commercial ASIC CAD toolflow

• Create new baseline and alternative designs at the register-transfer level, the associated effective testing strategies, and a thorough evaluation plan

• Write comprehensive technical reports that describe designs implemented at the register-transfer level, explain the testing strategy used to verify functionality, and evaluate the designs to determine the superior approach

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This course aims to provide a strong foundation for students to understand the principle and practice of designing, implementing, testing, and evaluating complex standard-cell ASIC chips using automated state-of-the-art electronic design automation (EDA) tools. This course is at the intersection of computer architecture, digital circuits, and EDA and is suitable for students pursuing careers in both research and industry. For students pursuing research topics in computer architecture, the course will provide deeper insight into critical physical design issues for future computing systems, while for students pursuing research topics in digital circuits, the course will provide system-level insight into future large-scale chip designs. For students pursuing a career in the chip-design industry, the course will provide valuable design experience from architecture to digital circuits. The course is divided into four parts: the first three parts are lecture-based, while the final part is an extensive design project. The first part provides an overview of ASIC design including: hardware description languages; CMOS devices; CMOS circuits; full-custom design methodology; automated design methodologies; testing and verification; packaging and I/O. The second part provides a deeper study of CMOS digital-circuit fundamentals including combinational logic, sequential state, and interconnect. The third part provides a deeper study of EDA algorithms including synthesis algorithms and physical design automation algorithms. The final part is an open-ended design project where small groups of students design, implement, test, and evaluate an interesting technique in computer architecture using functional-, microarchitectural-, register-transfer-, and layout-level modeling. This five-week long design experience will include weekly project meetings with the course instructors, milestone documents, a project demonstration, and a detailed final report.

Course Type: Formal

People

Organisations: Cornell University

Creators:	Christopher Batten

Certification

Course Structure

Delivery Mode: Face-to-Face

Length: 4 months

Assessment: The final grade is calculated using a weighted average of all assignments with the following distribution:Lab Assignment 1 10% Lab Assignment 2 15% Midterm 30% Design Project Milestones 10% (evenly weighted) Design Project Demonstration 10% Design Project

Taxonomy

Subjects: Design Flow > Behavioural Design

Other

Course URL: https://www.csl.cornell.edu/courses/ece5745/syllabus.html

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