Verilog

Verilog is a hardware description language used by designers to describe electronic systems. It allows the designer to define in a formal notation their proposed hardware. Various activities in the hardware design and verification process use the description as input. For example operating the hardware design in a computer simulation environment to help verify it will operate as expected when fabricated. The language is initially standardised via IEEE standard 1364 but later became part of SystemVerilog under IEEE standard 1800.