Description:
Our Introduction to Computer Architecture Education Kit equips your students with the fundamental concepts of computer architecture and how these concepts are applied and implemented in modern processors. This kit is suitable for introductory and mid-level computer architecture courses in Electronic and Computer Engineering, and Computer Science. Lab manual with solutions for faculty are available upon request from https://www.arm.com/resources/education/education-kits/aup-donation-request-form
Organisations: Arm Education
Target Audience
This kit is suitable for introductory and mid-level computer architecture courses in Electronic and Computer Engineering, and Computer Science.
Learning Aims:
Knowledge and understanding of
- The fundamentals of computer design including a simple processor and instruction set architecture, and outline key features of Arm instruction set architectures.
- The component functions, benefits and drawbacks of a superpipelined and superscalar processor in computer architecture design.
- The function, types, and hierarchies of memory in computer architecture design.
- The purpose, function, types and performance classifications of a cache in computer architecture design.
- The function of multicore processors including the related concepts of multicore communication, cache coherence and memory consistency.
- The function, benefits and drawbacks of multithreading including the related concepts of multitasking, fine-grained multithreading, coarse-grained multithreading and simultaneous multithreading.
- The function and benefits of data-level parallelism as a computer architecture choice including vector processors,
- Single Instruction, Multiple Data (SIMD) and Graphics Processing Units (GPUs).
Intellectual
- Describe what is meant by 'computer architecture' and discuss historical and future computer architecture trends.
- Explain the implementation of basic processor pipelining including assessing hazards and performance.
- Explain the implementation of advanced processor pipelining including branch handling, handling exceptions and the limitations of pipelining.
- Explain the building blocks, main features, design considerations and benefits of modern System-on-Chip (SoC) design.
Practical
- Utilize tool commands and example code to ensure successful set up of software tools for the labs including Icarus Verilog, GNU Toolchain for the A-profile Architecture (contains GCC compiler), and GTKWave.
- Write assembly code using a subset of Armv8-A AArch64 instructions and simulate on a simple processor called the Arm Education Core.
- Categorize the encodings of a subset of the Armv8-A instruction into specific fields to interpret instruction operations.
- Demonstrate the functionality and behavior of key components in the Instruction Fetch and Instruction Decode stages using the Arm Education Core.
- Demonstrate the functionality and operation of key components in the Execution, Memory Access, and WriteBack stages using the Arm Education Core.
- Implement a simple pipeline using the Arm Education Core.
- Implement forwarding paths to resolve Read-After-Write (RAW) data hazards using the Arm Education Core.
- Implement a stall and control hazard solution using the Arm Education Core, and estimate Power, Performance, and Area.
README.md
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README.md
![[thumbnail of Module_2_Fundamentals_of_computer_design.pptx]](https://compedulabs.org/style/images/fileicons/slideshow.png)
Module 2: Fundamentals of Computer Design
![[thumbnail of Module_3_Pipelining.pptx]](https://compedulabs.org/style/images/fileicons/slideshow.png)
Module 3: Pipelining
![[thumbnail of Module_4_Branches_and_the_limits_to_pipelining.pptx]](https://compedulabs.org/style/images/fileicons/slideshow.png)
Module 4: Branches and the Limits to Pipelining
![[thumbnail of Module_5_Exploiting_instruction-level_parallelism.pptx]](https://compedulabs.org/style/images/fileicons/slideshow.png)
Module 5: Exploiting Instruction-Level Parallelism
![[thumbnail of Module_6_Memory.pptx]](https://compedulabs.org/style/images/fileicons/slideshow.png)
Module 6: Memory
![[thumbnail of Module_7_Caches.pptx]](https://compedulabs.org/style/images/fileicons/slideshow.png)
Module 7: Caches
![[thumbnail of Module_8_Multicore.pptx]](https://compedulabs.org/style/images/fileicons/slideshow.png)
Module 8: Multicore
![[thumbnail of Module_9_Mulithreading.pptx]](https://compedulabs.org/style/images/fileicons/slideshow.png)
Module 9: Multithreading
![[thumbnail of Module_10_Vector__SIMD__GPUs.pptx]](https://compedulabs.org/style/images/fileicons/slideshow.png)
Module 10: Vector, SIMD, GPUs
![[thumbnail of Module_11_SoC_Study.pptx]](https://compedulabs.org/style/images/fileicons/slideshow.png)
Module 11: SoC Case Study
Our Introduction to Computer Architecture Education Kit equips your students with the fundamental concepts of computer architecture and how these concepts are applied and implemented in modern processors. This kit is suitable for introductory and mid-level computer architecture courses in Electronic and Computer Engineering, and Computer Science. Lab manual with solutions for faculty are available upon request from https://www.arm.com/resources/education/education-kits/aup-donation-request-form
Course Type: Open
People
Organisations: Arm Education
Creators: | Mark Allen |
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Contributors: | GitHub Contributor: | David Mackenzie |
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GitHub Contributor: | Catan Francis | |
GitHub Contributor: | Liz Warman | |
GitHub Contributor: | Mark Allen |
Certification
Course Structure
Taxonomy
Interests: Radio Frequency Design , Thumb instruction set , Synchronous Dynamic Random Access Memory (SDRAM)
Other
Course URL: https://github.com/arm-university/Introduction-to-Computer-Architecture-Education-Kit
Discussion